Description

Lead ASIC IP verification for high-speed I/O protocols, owning the testbench architecture, coverage convergence, and silicon debug support.

This role is on-site.

Responsibilities

• Build UVM-based testbenches with directed and random test cases to validate functionality, performance, and product use cases.
• Collaborate with architects, hardware, and firmware engineers to define product requirements for FPGA and ASIC IP.
• Debug test failures, drive bug-finding activities, and ensure coverage convergence for zero-defect design implementation.
• Provide silicon debug support to partner validation teams throughout the development lifecycle.
• Leverage AI technologies to optimize verification workflows and improve automation efficiency.

Required Skills

• 10+ years of experience in IP-level ASIC verification.
• Strong proficiency in SystemVerilog, UVM, and Verilog.
• Deep knowledge of PCIe and CXL protocols.
• Hands-on experience with DMA verification.
• Proficiency in Linux and Windows environments.
• Experience with Perl scripting.

Preferred Skills

• Exposure to AI/LLMs in verification, HLS tools, and simulation profiling.
• Leadership and mentorship experience.
• Shell scripting and Makefile scripting skills.

Key Skills

Education

Any Graduate