Description

Lead pre-silicon verification for IP blocks and subsystems, managing the full validation lifecycle from planning to coverage closure.

Responsibilities

• Develop verification plans for IP blocks and subsystems based on design specifications.
• Lead a team of verification engineers using industry-standard methodologies and tools.
• Oversee creation of verification environments and testbenches using SystemVerilog and UVM.
• Guide team in writing and executing test cases to verify functionality, performance, and compliance.
• Define and track functional, code, and assertion coverage metrics while debugging verification failures.

Required Skills

• Several years of experience in pre-silicon verification of IP blocks and subsystems.
• Proven experience in a leadership or lead role.
• Proficiency in SystemVerilog and UVM, OVM, or constrained random testing.
• Strong programming skills in SystemVerilog, C/C++, Perl, or Python.
• Experience with industry-standard tools such as Synopsys VCS, Cadence Incisive, or Mentor Questa.
• Ability to analyze coverage metrics including functional, code, and assertion coverage.
• Strong analytical skills for debugging and optimizing verification processes.
• Understanding of semiconductor industry standards and protocols.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Key Skills

Education

Any graduate