Description

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs, driving end-to-end testability and silicon debug.

This role is remote.

Responsibilities

• Drive scan architecture, insertion, chain stitching, and compression workflows to achieve high coverage and robust testability.
• Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
• Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
• Develop and validate DFT constraints, including DFT SDC, timing checks, and specific timing analysis.
• Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills

• 5+ years of hands-on experience in ASIC DFT with end-to-end ownership.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
• Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
• Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
• Experience with DFT SDC creation and DFT timing closure support.
• Proficiency in TCL, Perl, and Python scripting.

Preferred Skills

• SMS experience and Tessent/SSN proficiency.
• Post-silicon validation and manufacturing test optimization.
• Familiarity with yield learning and diagnosis methodologies.

Key Skills

Education

Bachelor's degree