Description

Key Skills: ASIC Design Verification, SystemVerilog, C/C++, x86 Architecture, Cache Verification, Coverage Planning, Test Planning, Low Power Verification, Microprocessor ISA, Power Management

Good to Have Skills: ARM architecture experience, coherency and data-consistency verification, clocking and reset verification, design-for-debug (DFD) logic knowledge, microprocessor design experience, and familiarity with advanced technology nodes.

Roles & Responsibilities:

• Verification of high performance x86-core ISA features for next-generation processors.
• Architecting and development of testbench and test-bench components for high performance cache and processor features.
• Development of detailed test plans and driving the execution of test plan including functional coverage.
• Understanding the existing test bench setup and look for opportunities to improve the existing test bench.
• Adhering to coding guideline practices, develop and implement code review process for verification components.
• Collaborate with global design verification teams and drive effectively the execution of the verification plans.
• Demonstrate commitment to innovating as a team through excellent communication and independently driving tasks to completion.

Experience Required: 8 to 12 years of ASIC design verification experience with strong understanding of design and verification life cycle. Hands-on verification experience with C/C++/SystemVerilog testbench development and coverage planning, coding and coverage closure.

Education: Master's degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

Key Skills

Education

Any Graduate