Description

You will lead DFT activities focusing on scan design, clock architecture, and ATPG methodology.

Responsibilities

• Execute ATPG test pattern generation for stuck-at and at-speed faults at both block and SoC levels.
• Perform depth fault coverage analysis to identify and resolve issues to meet coverage targets.
• Implement test compression and decompression scan methodologies.
• Manage boundary scan test planning and coverage using JTAG.
• Integrate MBIST at the partition and SoC levels, including memory redundancy logic.

Required Skills

• 8+ years of experience in DFT engineering.
• Expertise in Scan design and Clock architecture.
• Proven experience with ATPG methodology and industry standard tools.
• Strong understanding of MBIST concepts and insertion.
• Knowledge of JTAG and all relevant IEEE JTAG standards.
• Proficiency in scripting using TCL, Perl, or Python.
• Experience generating test patterns at block and SoC levels.
• Any Graduate degree.

Key Skills

Education

Any Graduate