Description

You will lead the verification of complex digital design blocks, ensuring production-ready quality through rigorous testing and analysis.

Responsibilities

• Architect and build SystemVerilog/UVM testbenches to verify complex digital design blocks.
• Collaborate with architects and design engineers to create comprehensive verification testplans.
• Develop constrained-random and directed verification environments, including formal verification using SystemVerilog Assertions.
• Debug functional issues with design engineers and drive verification closure on coverage metrics.
• Identify verification holes and implement coverage measures to ensure stimulus quality and completeness.

Required Skills

• 8+ years of experience in verification engineering with deep expertise in UVM and SystemVerilog.
• Strong background in digital design verification and understanding of architecture specifications.
• Proficiency in creating and enhancing testbenches for complex digital blocks.
• Experience with formal verification methodologies and SystemVerilog Assertions (SVA).
• Familiarity with simulation tools such as Synopsys VCS or Cadence IES.
• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Key Skills

Education

Any Graduate