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Lead IP Verification Engineer

CareerNet Technologies Pvt Ltd

 

Hyderabad, Telangana, India

Posted On: 10 days ago
Experience: 8+ years
Availability: Onsite
Openings: 1
Category: Verification Engineer
Tenure: No Preference/Any
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Description

Lead verification of complex digital design blocks, ensuring production-ready quality through rigorous testing and analysis.

This role is on-site.

Responsibilities

  • Architect and build SystemVerilog/UVM testbenches for complex digital design blocks.
  • Collaborate with architects and design engineers to create comprehensive verification test plans.
  • Develop constrained-random and directed verification environments, including formal verification using SystemVerilog Assertions.
  • Debug functional issues with design engineers and drive verification closure on coverage metrics.
  • Identify verification holes and implement coverage measures to ensure stimulus quality and completeness.

Required Skills

  • 8+ years of experience in verification engineering.
  • Deep expertise in UVM and SystemVerilog.
  • Strong background in digital design verification and understanding of architecture specifications.
  • Proficiency in creating and enhancing testbenches for complex digital blocks.
  • Experience with formal verification methodologies and SystemVerilog Assertions (SVA).
  • Familiarity with simulation tools such as Synopsys VCS or Cadence IES.
  • Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Education

Any Graduate

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