Lead IP Verification Engineer

Key Skills: System Verilog, UVM, Verification, Digital Design, SystemVerilog Assertions (SVA), Formal Verification, Coverage Analysis, Network on Chip (NOC)

Good to Have Skills: Experience with OVM, VMM test benches, simulation tools like Synopsys VCS, Cadence IES, AXI3/4 protocols, DDR4/5, HBM, PCIe, processors, graphics verification, gate level simulation, power verification, reset verification, formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan), verification management tools, database management for regression management.

Roles & Responsibilities:

• Lead and plan verification of complex digital design blocks by fully understanding the architecture and design specifications.
• Interact with architects and design engineers to create a comprehensive verification testplan for project execution.
• Design and architect testbenches in System Verilog and UVM to complete verification of the design efficiently.
• Create and enhance constrained-random and directed verification environments, and formally verify designs with SystemVerilog Assertions.
• Debug tests with design engineers to deliver functionally correct design blocks for production readiness.
• Identify and write coverage measures for stimulus quality improvements and verification completeness assessment.
• Perform coverage analysis to identify verification holes and achieve closure on coverage metrics for quality assurance.

Experience Required: 8+ years of experience in verification engineering with expertise in UVM, System Verilog, and digital design verification.

Education: Bachelor's or Master's degree in Computer Engineering or Electrical Engineering