Description

Responsibilities include:

Develop and enhance performance-monitoring tools to analyze SoC behavior, cache utilization, memory bandwidth, and on-die interconnect performance.

Monitor and characterize L2/L3 cache traffic, network-on-chip (NoC) communication, and resource contention across Intel-based platforms.

Establish and validate QoS policies, bandwidth allocation limits, channel priorities, and arbitration mechanisms to optimize system performance.

Perform LLC occupancy, memory-controller bandwidth, and inter-core interference analysis using Intel PMU and uncore performance counters.

Investigate cache and fabric contention issues, identify performance bottlenecks, and provide recommendations to improve latency and throughput.

Create and maintain automated performance-analysis frameworks for Intel Tiger Lake, Ice Lake, Alder Lake, and Xeon platforms to support system optimization and certification efforts.

Required Qualifications:

Bachelor’s degree in computer engineering, Computer Science, Electrical Engineering, or a related technical discipline.

8+ years of hands-on experience in SoC performance analysis, platform performance engineering, or CPU architecture performance optimization.

Proven experience with Intel Tiger Lake, Ice Lake, Alder Lake, Xeon platforms, and Intel PMU/uncore performance counters for cache and memory subsystem analysis.

Strong expertise in Last Level Cache (LLC) characterization, QoS enforcement, bandwidth allocation, cache allocation technology (CAT), and memory bandwidth allocation (MBA)

Key Skills

Education

Any Graduate