Description

You will develop memory compilers and memory Fast Cache instances for next-generation cores to achieve target PPA.

Responsibilities

• Develop memory compilers and Fast Cache instances for next-generation cores.
• Optimize designs for Power, Performance, and Area (PPA) trade-offs.
• Execute SRAM and memory design margin, characterization, and quality checks.
• Implement high-speed and low-power CMOS circuit designs and clocking schemes.

Required Skills

• 5+ years of experience in SRAM or memory design.
• Strong understanding of computer architecture and concepts.
• Deep knowledge of CMOS transistors and their behaviors.
• Experience with high-speed/low-power CMOS circuit design and complex logic circuits.
• Proficiency in circuit design and reliability analysis.
• Foundational knowledge of physics and CMOS design trade-offs.
• Ability to work with standard cell circuit simulation and optimization.

Preferred Skills

• Experience with scripting languages including Perl, Tcl, or Python.
• Experience using Cadence or Synopsys design flows.

Key Skills

Education

Any Graduate