Description

Lead the development and verification of memory compiler layouts for SRAM designs.

This role is on-site.

Responsibilities

• Develop layouts for SRAM memory blocks, including arrays, decoders, sense amplifiers, and control blocks.
• Perform physical verification tasks including DRC, LVS, latch-up, and quality checks.
• Execute floor planning, power planning, and block area estimation for memory designs.
• Manage project schedules through area/time estimation, task delegation, and technical execution.
• Guide junior team members by reviewing sub-block level layouts and providing technical support.

Required Skills

• 3+ years of experience in SRAM memory layout design.
• Expertise in custom memory bits, leaf cells, control blocks, read-write circuits, and decoders.
• Proficiency with Cadence Virtuoso (Schematic Editor, Layout, XL) and Mentor Calibre.
• Strong understanding of layout fundamentals: electromigration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, and shielding.
• Ability to interface with circuit designers and CAD/process development teams using schematic knowledge.
• Experience in physical verification, DRC, and LVS.
• Knowledge of layout effects on speed, capacitance, power, and area.

Preferred Skills

• Knowledge of Skill coding and layout automation.

Key Skills

Education

Any Graduate