Memory Layout Engineer

You will lead the development and verification of memory compiler layouts.

Responsibilities

• Develop layouts for SRAM memory blocks, including arrays, row/column decoders, sense amplifiers, pre-charge, and control blocks.
• Perform physical verification tasks including DRC, LVS, latch-up, and quality checks.
• Execute floor planning, power planning, and block area estimation for memory designs and compilers.
• Manage project schedules through area/time estimation, task delegation, and technical execution.
• Guide junior team members by reviewing sub-block level layouts and providing technical support.

Required Skills

• 3+ years of experience in SRAM memory layout design.
• Expertise in custom memory bits, leaf cells, control blocks, read-write, sense amplifiers, and decoders.
• Proficiency with Cadence Virtuoso (Schematic Editor, Layout L, XL) and Mentor Calibre.
• Strong understanding of layout fundamentals: electro-migration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, and shielding.
• Ability to interface with circuit designers and CAD/process development teams using schematic knowledge.
• Experience in physical verification, DRC, and LVS.
• Knowledge of layout effects on speed, capacitance, power, and area.
• Proven ability in device matching, parasitic analysis, and isolation techniques.
• Strong problem-solving skills regarding area, power, and performance.

Preferred Skills

• Knowledge of Skill coding and layout automation.