Description

You will lead the layout development and verification of memory compilers and individual memory blocks.

Responsibilities

• Develop layouts for memory blocks including arrays, row/column decoders, sense amplifiers, pre-charge, and SRAM control blocks.
• Execute layout verification tasks such as LVS, DRC, and latch-up checks, including quality documentation.
• Manage block-level layout delivery timelines, area estimation, and scheduling across multiple projects.
• Guide junior team members through sub-block level layout execution and technical reviews.
• Collaborate with circuit designers, CAD, and process development teams to ensure design success.

Required Skills

• 5+ years of experience in custom memory layout development.
• Expertise in floor planning, power planning, and block area estimation for memory compilers.
• Proficiency with Cadence Virtuoso (Schematic Editor, Layout L, XL) and Mentor Calibre for verification.
• Deep understanding of layout fundamentals: electromigration, latch-up, coupling, crosstalk, IR-drop, and parasitic analysis.
• Hands-on experience with device matching, isolation techniques, and shielding.
• Ability to analyze layout effects on speed, capacitance, power, and area.
• Experience performing leaf cell layout development and physical verification.
• Strong technical communication skills for coordinating with global engineering teams.

Preferred Skills

• Knowledge of SKILL coding and layout automation.

Key Skills

Education

Any Graduate