Description

You will design and develop microarchitecture for CPU cores, accelerators, memory subsystems, and SoC components.

This role is on-site.

Responsibilities

• Design and optimize pipeline structures, including instruction fetch, decode, execute, and memory access stages.
• Develop cache hierarchies, coherence protocols, and prefetching mechanisms to improve data locality.
• Implement on-chip interconnects such as buses, crossbars, and networks-on-chip (NoCs).
• Integrate power management techniques like clock gating, power gating, and DVFS.
• Collaborate with verification engineers to validate designs via simulation, emulation, and hardware prototyping.

Required Skills

• Extensive experience in microarchitecture design, CPU design, or SoC design.
• Strong proficiency in C/C++.
• Hands-on experience with Python and scripting languages for design automation and modeling.
• Deep understanding of Instruction Set Architecture (ISA) and pipeline stages.
• Expertise in designing L1, L2, and L3 cache hierarchies and replacement policies.
• Knowledge of industry-standard tools including Verilog, VHDL, SystemVerilog, Cadence, Synopsys, and Mentor tools.
• Ability to analyze complex design bottlenecks and propose architectural solutions.

Key Skills

Education

Any graduate