Description

You will design and develop microarchitectures for highly configurable IPs, owning the path from architecture definition through RTL implementation.

This role is on-site.

Responsibilities

• Design and develop microarchitectures for a set of highly configurable IPs.
• Perform microarchitecture and RTL coding to ensure optimal performance, power, and area.
• Collaborate with software teams to define configuration requirements and verification collateral.
• Work with verification teams on assertions, test plans, debug, and coverage.

Required Skills

• 8+ years of hands-on experience in microarchitecture and RTL development.
• Proficiency in Verilog and SystemVerilog.
• Experience with large, high-speed, pipelined, stateful, and low-power designs.
• In-depth understanding of on-chip interconnects and NoCs.
• Experience with Arm ACE/CHI or similar coherency protocols.
• Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects, and NoCs.
• Familiarity with industry-standard EDA tools and methodologies.
• BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.

Preferred Skills

• Familiarity with RAS designs, QoS in fabrics, and PCIe/IO.
• Experience with Python.

Key Skills

Education

Any Graduate