Description

You will own the development and verification of analog and mixed-signal models to ensure functional specification compliance.

Responsibilities

• Extract modeling specifications from designers to develop Analog/Mixed-Signal models in SystemVerilog.
• Build UVM testbenches and develop comprehensive test cases for digital and AMS simulators.
• Run simulations and collaborate with circuit designers to fix behavioral model errors.
• Develop timing models for circuits in coordination with layout engineers.
• Influence design changes to meet functional specifications and support the integration of composite models.

Required Skills

• 5+ years of experience in mixed-signal verification.
• Strong SystemVerilog RTL coding skills, including state machines, adders, multipliers, and combinatorial logic.
• Experience designing Verilog/Verilog-A code to control analog circuits such as bandgap, PLL, amplifiers, filters, and CDR.
• Proficiency in writing behavioral Verilog code for analog circuits.
• Ability to write thorough testbenches for digital and AMS simulators.
• Deep understanding of mixed-signal constraints, multiple clock domains, and clock gating.
• Familiarity with timing closure and static timing analysis tools.
• Experience with scan chain vector generation and verification.
• Proficiency with Python and Synopsys tools.

Key Skills

Education

Any Graduate