Description

Lead chip-level physical design and implementation from netlist to GDSII.

Responsibilities

• Execute chip-level floor planning, partitioning, timing budget generation, and power planning.
• Own top-level Place and Route (PnR), Clock Tree Synthesis (CTS), block integration, and ECO generation.
• Manage timing closure (STA) for high-frequency blocks and complex designs exceeding 1M instances at 1GHz+.
• Implement low power strategies including power gating, multiple voltage rails, and UPF.
• Drive signoff closure for timing (with SI and OCV), power, IR, and physical verification at block and chip levels.

Required Skills

• 8+ years hands-on experience in block/chip level implementation from netlist to GDSII.
• Proven tape-out experience in advanced technology nodes (3nm, 5nm, 7nm, 10nm, or 16nm).
• Proficiency with Synopsys Fusion Compiler, ICC/ICC2, or Cadence EDA Tool Suite.
• Expertise in Static Timing Analysis (STA), PrimeTime-SI, and PnR methodologies.
• Experience with Signal Integrity (SI) prevention, fixing methodology, and layout edit techniques.
• Ability to handle blocks with 1M+ instances and frequencies above 1GHz.
• Strong debug and analytical skills for resolving design and timing issues.
• Experience working within UNIX environments.

Preferred Skills

• Scripting proficiency in Tcl/Tk, Perl, or Python.
• Experience with Synthesis and Formal verification.

Key Skills

Education

Any Graduate