Description

You will define and execute performance verification scenarios for chip architecture, identifying bottlenecks and optimization opportunities across TLM, RTL, emulation, and silicon validation.

This role is on-site.

Responsibilities

• Develop performance verification scenarios to test design architecture and stress target paths, features, and subsystems.
• Create test cases covering system scenarios and benchmarks using industry standards and inputs from architecture, software, and IP teams.
• Perform debug, failure re-creation, and root cause analysis to resolve performance issues.
• Correlate performance metrics across TLM, RTL, Emulation, Silicon validation, and applications.

Required Skills

• 5+ years of experience in performance or verification engineering.
• Proficiency with HDL/HDL including Verilog and SystemVerilog.
• Hands-on experience with UVM methodology and VIP monitors.
• Strong understanding of bus protocols such as AHB, AXI, NIC, ACE, and NOC.
• Knowledge of processor architecture, debug architecture, and cache coherency.
• Understanding of memory subsystems, caches, and DDR controllers.
• Programming proficiency in C, C++, or Python.

Preferred Skills

• Experience executing, analyzing, and debugging test cases on emulation platforms.
• Domain knowledge in Graphics, Multimedia, or Networking IPs such as PCIe, MIPI, Ethernet, or USB.

Key Skills

Education

Any Gradute