Description

Execute block and chip-level implementations across various process nodes, managing physical design from Netlist to GDSII at the IP or SOC level.

Responsibilities

• Manage physical design implementation from Netlist to GDSII at the IP or SOC level.
• Partner with cross-functional design teams to define and develop ASIC physical designs.
• Drive the definition of flows, methodologies, and tool selection to improve closure processes.
• Execute timing closure and physical verification to meet tape-out schedules.
• Apply quick solutions and work-arounds during tape-out phases to ensure timely delivery.

Required Skills

• Hands-on experience with block or chip-level implementation from Netlist to GDSII.
• Proven tape-out experience using ICC/ICC2, Fusion Compiler, or Innovus.
• Direct experience working with lower tech nodes including 7nm, 10nm, 16nm, 28nm, and 40nm.
• Strong expertise in timing closure and physical verification closure.
• Proficiency in scripting with TCL, Perl, or Python.
• BTech/MTech in Microelectronics, Electrical Engineering, Computer Science, or a related Science field.
• 5 to 12+ years of relevant industry experience.

Preferred Skills

• Experience in Synthesis and Formal verification.

Key Skills

Education

Any Graduate