Description

You will own the physical design flow for complex SoC designs, driving timing closure, integrity analysis, and tape-out readiness.

This role is on-site.

Responsibilities

• Lead and execute Static Timing Analysis (STA) closure across multiple corners and modes for complex digital designs.
• Perform Signal Integrity (SI) and Power Integrity (PI) analysis to resolve crosstalk and IR drop issues.
• Develop chip finishing strategies and ECO flows to ensure successful tape-out.
• Drive Design for Manufacturing (DFM) initiatives by optimizing physical layouts.
• Improve STA methodologies and scripting flows for efficiency and accuracy.

Required Skills

• 5+ years of experience in STA closure for complex digital designs.
• Proven expertise in Signal Integrity (SI) and Power Integrity (PI) analysis.
• Strong knowledge of chip finishing methodologies, timing sign-off, and tape-out processes.
• Understanding of physical design concepts: floorplanning, placement, and routing.
• Proficiency with PrimeTime and Tempus for STA and timing analysis.
• Scripting proficiency in Tcl, Python, and Perl.
• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.

Key Skills

Education

Bachelor's degree