Description

You will execute the full physical design flow for complex integrated circuits from floorplanning through to physical verification.

Responsibilities

• Develop floorplans that satisfy area, power, and performance requirements.
• Execute block-level and chip-level placement and routing to optimize signal integrity and minimize area.
• Design and optimize clock distribution networks (CTS) and power distribution networks (PDN) to manage skew and IR drop.
• Perform physical verification including DRC and LVS checks to ensure layout compliance.
• Drive timing closure using static timing analysis (STA), clock skew optimization, and buffer insertion.

Required Skills

• 4-8 years of experience in physical design of complex ICs using leading-edge technologies.
• Proficiency with industry-standard tools including Cadence Innovus, Synopsys ICC, and Mentor Calibre.
• Deep understanding of the complete physical design flow: floorplanning, placement, routing, CTS, and PDN.
• Expertise in timing closure techniques, including STA and hold time fixing.
• Hands-on experience with Design for Manufacturability (DFM) and yield enhancement methodologies.
• Scripting proficiency in Tcl, Perl, or Python for design automation.
• Strong analytical skills for solving complex physical design challenges.

Preferred Skills

• Experience working with CAD engineers and cross-functional design teams.

Key Skills

Education

Any graduate