Description

You will own the physical implementation of multimillion gate SoC designs using FinFET process technologies at 16nm, 14nm, and below.

Responsibilities

• Execute synthesis, Place & Route, and timing closure to optimize PPA.
• Perform floorplanning and power grid design to meet EMIR specifications.
• Generate and implement ECOs to resolve timing, noise, and EMIR violations.
• Manage analog/custom block integration by creating LEF/DEF files, defining pins/ports, and merging databases into Cadence Virtuoso.
• Maintain hierarchy for extraction and verification through the P&R database.

Required Skills

• 4+ years of relevant experience in physical design.
• Expertise in FinFET technologies (16nm, 14nm, and below).
• Proficiency with Cadence, Synopsys, and Mentor EDA tools.
• Strong understanding of timing concepts, digital logic design, CMOS, and device physics.
• Experience with low-power UPF flows.
• Knowledge of mixed-signal layout matching: interdigitation, common centroid, dummies, bypass capacitor design, and star connection power supply bus construction.
• Experience with critical route shielding, triple well layout, ESD device/cell layout, and guard ring methods.
• Bachelor of Engineering or ME/M.Tech degree.

Preferred Skills

• Scripting experience in Tcl, Perl, Shell, or Python.
• Experience with Mentor Calibre DRC/LVS/PERC and Apache Totem EM & IR analysis.

Key Skills

Education

Any Graduate