Description

You will manage the complete physical design flow from floorplanning through to tape-out.

Responsibilities

• Execute placement, floorplanning, and Clock Tree Synthesis (CTS).
• Perform Static Timing Analysis (STA) to ensure timing closure.
• Manage physical verification processes including antenna checks, ERC, and DFM.
• Drive DRC and LVS closure to meet sign-off requirements.
• Coordinate with Circuit Designers and RTL Engineers to facilitate project success.

Required Skills

• 4 to 12 years of experience in physical design.
• Proficiency with Synopsys ICC, Fusion Compiler (FC), or Cadence Innovus and Encounter.
• Experience with Cadence Tempus for timing analysis.
• Hands-on work with advanced technology nodes: 3nm, 5nm, 7nm, and 10nm.
• Strong knowledge of the complete physical design flow and STA.
• Scripting proficiency in Tcl, Perl, and Python.
• Ability to achieve DRC and LVS closure.
• Any Graduate degree.

Preferred Skills

• Prior experience with tape-out at client sites.

Key Skills

Education

Any Graduate