Description

You will own physical design implementation for high-performance IPs, from placement through timing closure and verification.

Responsibilities

• Execute placement, clock tree synthesis (CTS), and static timing analysis (STA) in advanced technologies.
• Drive timing closure using STA tools, addressing OCV, AOCV, and statistical timing issues.
• Implement power grids, clock trees, and low-power reduction methodologies.
• Perform physical verification, Conformal Low Power (CLP), IR drop analysis, and formal verification.
• Coordinate with cross-functional teams to deliver IP environments and resolve signal integrity challenges.

Required Skills

• 8-12 years of experience in physical design, including at least 5 years of industry experience.
• Proficiency with STA tools and timing closure methodologies.
• Experience with Conformal Low Power (CLP), IR drop analysis, and formal verification.
• Strong programming and scripting skills in Tcl, Perl, and/or C.
• Ability to manage power grid and clock tree implementation.
• Experience addressing signal integrity and statistical timing issues.
• Bachelor's degree in Electrical Engineering.

Preferred Skills

• Experience with PPPA analysis, technology comparison, and semi-custom design of structured blocks.
• Knowledge of PnR tool limitations and power grid trade-offs.

Key Skills

Education

Any Graduate