Description

You will execute backend VLSI design flows for high-performance ASICs, SoCs, and custom silicon at block and top levels.

This role is on-site.

Responsibilities

• Execute floorplanning, partitioning, and macro placement while performing congestion analysis and power grid definition.
• Manage placement, legalization, and optimization to improve area, power, and timing.
• Design and optimize low-skew, high-performance clock trees and power delivery networks.
• Drive timing closure by resolving setup/hold violations, signal integrity issues, and crosstalk using static timing analysis.
• Handle routing, DRC closure, and sign-off verification including netlist-to-GDSII implementation.

Required Skills

• 5+ years of experience in Physical Design.
• Expertise in floorplanning, placement, and routing.
• Proficiency in Clock Tree Synthesis (CTS) and power distribution networks.
• Experience with Static Timing Analysis (STA) and timing closure.
• Strong scripting skills for design automation.
• Knowledge of physical verification methodologies and DRC closure.
• Experience with IR drop and electromigration (EM) analysis.
• Ability to manage hierarchical design and top-level layout planning.

Key Skills

Education

Any Gradute