Description

You will manage the end-to-end physical implementation process from netlist to GDSII for complex, high-frequency designs.

Responsibilities

• Execute chip-level floorplanning, partitioning, power planning, and top-level PnR.
• Drive timing closure (STA) for high-frequency blocks and manage CTS and block integration.
• Handle low-power implementation including power gating, multiple voltage rails, and UPF.
• Manage signoff closure for timing (SI and OCV), power, IR, and physical verification at both block and chip levels.
• Perform layout edit techniques and generate ECOs to meet tape-out schedules.

Required Skills

• 10+ years of hands-on experience in block and chip-level implementation.
• Proven tape-out experience in advanced technology nodes (3nm, 5nm, 7nm, 10nm, or 16nm).
• Experience handling large-scale designs with 1M+ instances and clock frequencies above 1GHz.
• Proficiency with Synopsys Fusion Compiler, ICC/ICC2, Cadence Innovus, or PTSi.
• Deep understanding of SI prevention, fixing methodologies, and constraint management.
• Expertise in timing closure, physical verification, and low-power signoff.
• Strong debugging and analytical skills for independent problem-solving.
• Proficiency in UNIX systems.
• Strong scripting capabilities in TCL/Tk, Perl, or Python.

Preferred Skills

• Experience with Synthesis and Formal verification.

Key Skills

Education

Any Gradute