Key Responsibilities

• Floorplanning and macro placement
• Placement optimization
• Clock Tree Synthesis (CTS)
• Routing and ECO implementation
• Timing closure support
• Congestion and utilization optimization
• DFM and signoff fixes
• Support tape-out activities

LONGDESCRIPTION section. 3 of 6.

Section Title: Skill Requirements

Skill Requirements

• ICC2/Fusion Compiler/Innovus expertise
• Understanding of ASIC implementation flow
• Timing analysis fundamentals
• CTS and routing concepts
• TCL, Perl, Python scripting
• LEF/DEF, Liberty, Verilog knowledge
• Basic understanding of IR/EM and Physical Verification