Description

Drive timing closure and signoff for high-speed, complex SoC designs across multiple clock and power domains.

Responsibilities

• Drive timing closure-friendly SoC architecture and IO interfaces/pin assignments in collaboration with Systems and Application teams.
• Streamline timing signoff criteria, analysis methodologies, and flows, including critical path spice simulation.
• Develop and enhance automated ECO generation scripts and STA scripts/flows.
• Incorporate advanced signoff flows such as SSTA, LOCV-based STA, and IR drop aware STA into the SoC flow.
• Analyze failures in functional and test gate-level simulations using back-annotated data.

Required Skills

• 2-10 years of experience in SoC, chip-level, or IP timing closure and signoff.
• Expertise in developing full chip timing constraints for complex, multi-clock, multi-voltage SoCs.
• Hands-on experience with Synopsys PrimeTime.
• Proven ability to achieve timing closure on high-performance and low-power designs.
• Knowledge of industry standard IO interfaces including DDR2, SDR, LPDDR, Flash, SPIs, USBHS, USBFS, JTAG, and Display.
• Experience developing and supporting fully automated STA scripts and flows.
• Ability to interact with Verification and DFT teams to resolve simulation failures.

Preferred Skills

• Experience improving the entire timing flow from pre-layout to post-layout at both chip and block levels.
• Participation in post-silicon validation, correlation, and test activities using in-house lab equipment.

Key Skills

Education

Any Gradute