Description

Own power integrity, electromigration, and IR drop analysis for block, subsystem, and SoC levels to ensure clean signoff.

This role is remote.

Responsibilities

• Perform static and dynamic IR drop analysis and close Power EM and Signal EM violations against foundry reliability rules.
• Support PDN design and optimization by recommending mesh, strap, and via enhancements.
• Run thermal analysis and correlate power, timing, and reliability results for final signoff.
• Collaborate with Physical Design teams during floorplanning, power planning, and routing to resolve escalations.
• Support silicon bring-up and late-stage signoff activities for power-related issues.

Required Skills

• 3+ years of experience in power integrity, EM/IR analysis, and reliability signoff for ASIC/SoC designs.
• Hands-on expertise with Voltus, RedHawk, RedHawk-SC, Totem, and PTPX.
• Ability to interpret rail drop, current density, hotspots, and reliability metrics to drive closure.
• Physical design awareness with integration context using ICC2 and Fusion Compiler.
• Proficiency in Python and Shell scripting for automation and analysis support.
• Tcl scripting experience for tool interaction and workflow automation.
• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.

Preferred Skills

• Experience with Innovus and PrimeTime for broader design and timing correlation workflows.
• Depth in RedHawk Thermal for advanced thermal analysis and reporting.

Key Skills

Education

Any Graduate