Description

Key Skills: Static Timing Analysis, Synthesis, RTL Design, CICD, Power automate

Roles and Responsibilities:

• Develop and maintain UPF power-intent files for power-efficient MCU and SoC designs.
• Define power domains, isolation, retention, level shifting, and power sequencing strategies.
• Support UPF methodology across RTL simulation, synthesis, STA, place and route, formal verification, and DFT flows.
• Automate UPF generation, validation, linting, and regression activities using Tcl and Python.
• Work closely with RTL, architecture, verification, and physical design teams on power-aware design practices.
• Guide teams on UPF standards, power architecture concepts, and low-power design methodologies.
• Develop documentation, sign-off reports, and handover packages for design and verification teams.
• Support CI/CD integration for automation and regression workflows.
• Troubleshoot and resolve power intent and low-power design issues.
• Contribute to process improvements and methodology standardization.

Skills Required:

• Strong experience in power architecture and power intent methodologies.
• Hands-on expertise in UPF (IEEE 1801) and low-power design concepts.
• Good understanding of RTL design, synthesis, and static timing analysis.
• Experience with Tcl and Python scripting for automation.
• Familiarity with ASIC/SoC design flows including verification and implementation.
• Exposure to CI/CD and automation workflows is an added advantage.
• Strong analytical, debugging, and communication skills.
• Ability to work collaboratively with cross-functional engineering teams.

Education: Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field

Key Skills

Education

Any Graduate