Description

Develop and maintain UPF power-intent files for power-efficient MCU and SoC designs.

This role is on-site.

Responsibilities

• Define power domains, isolation, retention, level shifting, and power sequencing strategies.
• Automate UPF generation, validation, linting, and regression activities using Tcl and Python.
• Support UPF methodology across RTL simulation, synthesis, STA, place and route, formal verification, and DFT flows.
• Troubleshoot and resolve power intent and low-power design issues.
• Contribute to process improvements and methodology standardization.

Required Skills

• 8+ years of experience in power architecture and power intent methodologies.
• Hands-on expertise in UPF (IEEE 1801) and low-power design concepts.
• Strong understanding of RTL design, synthesis, and static timing analysis.
• Experience with Tcl and Python scripting for automation.
• Familiarity with ASIC/SoC design flows including verification and implementation.
• Exposure to CI/CD and automation workflows.

Key Skills

Education

Any Graduate