Description

You will own power integrity simulations and PDN optimization for high-speed OSFP module designs.

This role is on-site.

Responsibilities

• Perform power integrity simulations using Ansys SIwave, Keysight ADS, and Cadence Sigrity to model PDN, targeting <1mO impedance across 10kHz-100MHz.
• Analyze and mitigate power rail decoupling, VRMs, and bypass capacitor placement for multi-rail supplies in high-current designs up to 100W+.
• Collaborate on PCB stack-ups, via optimization, and plane splitting to reduce simultaneous switching noise (SSN) and ground bounce in 112G PAM4 SerDes environments.
• Validate simulation results through lab measurements using VNAs, oscilloscopes, and power analyzers, correlating findings with hardware prototypes.
• Support signal integrity co-optimization and thermal-PDN synergy, ensuring compliance with IEEE 802.3ck and 802.3df standards.

Required Skills

• Strong hands-on experience with Power Integrity analysis and PDN optimization in high-speed designs.
• Proficiency in Ansys SIwave, Cadence Sigrity, and related PI/EMI analysis platforms.
• Experience with PCB stack-up design, decoupling strategies, and high-current multi-rail power systems.
• Knowledge of 112G PAM4 SerDes environments and electromagnetic interference mitigation techniques.
• Practical lab experience with oscilloscopes, VNA measurements, and power analyzers.
• Programming skills in Python for automation, data analysis, and simulation workflows.
• Bachelor's or Master's degree in Electrical or Electronics Engineering.

Preferred Skills

• Familiarity with MATLAB for modeling and validation.
• Experience mentoring junior engineers on best practices for hyperscale OSFP deployments.

Key Skills

Education

Any Graduate