Description

You will own the delivery of area-efficient, low-power, and high-performance micro-architecture for one or more functional IP blocks from specification to implementation.

Responsibilities

• Analyse proposed specifications to identify implementation challenges and collaborate with architects to refine designs.
• Plan, track, and coordinate tasks for yourself and your team.
• Work with modelling, verification, and back-end implementation teams to ensure designs meet functional and performance requirements.
• Develop and improve design methodologies to meet evolving technical needs.
• Make and articulate high-level design trade-offs for complex data path designs.

Required Skills

• 5+ years of experience in high-quality, low-power, and high-performance RTL design.
• Expertise in SystemVerilog, Verilog, or VHDL.
• Deep understanding of ASIC or FPGA design methodologies and IP signoff methods.
• Proven ability to manage timing, area, and complexity trade-offs for complex data path designs.
• Strong record of delivering sophisticated micro-architecture within reasonable timescales.
• Proficiency in scripting languages including Perl, Tcl, C shell, or Python.

Preferred Skills

• Team leadership and mentoring experience.
• Knowledge of memory system interconnect protocols such as AMBA ACE-Lite or AXI.
• Experience with SystemVerilog Assertions (SVA), formal verification, and hardware verification languages.

Key Skills

Education

Any Graduate