Description

You will lead complex hardware modeling and engineering initiatives for NPU architectures.

This role is on-site.

Responsibilities

• Lead the design, implementation, and maintenance of bit-accurate and cycle-accurate C/C++ hardware models.
• Define scalable modeling architectures that adapt to evolving hardware designs and microarchitecture updates.
• Design and develop software interfaces and APIs enabling software interaction with hardware models.
• Implement debugging, introspection, and tracing capabilities for deep model behavior analysis.
• Provide modeling infrastructure to support hardware–software co-verification and system-level validation.

Required Skills

• 5+ years of professional experience in complex technical roles.
• Expertise in C/C++ programming for hardware modeling and simulation.
• Strong understanding of NPU or AI accelerator architectures, memory systems, and dataflow.
• Proven experience with bit-accurate and cycle-accurate modeling and hardware–software co-design.
• Solid grounding in computer architecture and digital design principles.
• Experience with SystemC, transaction-level modeling (TLM).
• Proficiency in performance optimization and memory management for large-scale systems.

Preferred Skills

• Prior experience modeling AI accelerators, NPUs, GPUs, or similar compute architectures.
• Experience with FPGA prototyping, emulation, or hardware-in-the-loop validation.

Key Skills

Education

Any Gradute