← Back to jobs

Hays Logo
Principal Engineer - RTL Design

Hays

 

Bengaluru, Karnataka, India

Posted On: 30+ days ago
Experience: 12-18 years
Availability: Onsite
Openings: 1
Category: Principal Engineer
Tenure: No Preference/Any
Related Jobs

No related jobs found

Description

Lead the development of logic for complex compute subsystems and SoCs. You will own the release pipeline from micro-architecture specifications through RTL implementation.

Responsibilities

  • Write micro-architecture specifications and develop RTL for SoC projects.
  • Review architecture and develop detailed design specifications.
  • Fix bugs and execute various design checks throughout the development cycle.
  • Collaborate with verification teams to review test plans and debug design issues.
  • Partner with performance analysis teams to evaluate and improve subsystem performance.

Required Skills

  • 12-18 years of experience in the design of complex compute subsystems or SoCs.
  • Strong knowledge of digital hardware design and Verilog HDL.
  • Proven experience creating design specifications and developing RTL.
  • Proficiency in Perl, Python, or other scripting languages.
  • Thorough understanding of current design techniques for complex SoC development.
  • Bachelor's or Master's degree in Computer Science, Electrical Engineering, or Computer Engineering.

Preferred Skills

  • Experience with ARM-based designs or ARM System Architectures.
  • Experience integrating subsystems for PCIe, LPDDR, HBM, UCIe, or Ethernet.
  • Knowledge of SystemVerilog, UVM/OVM/e, CDC, and power management techniques.

Education

Bachelors or Master’s degree

Related Jobs

No related jobs found

← Back to jobs