Description

You will lead RTL design for complex SoC development and manage the end-to-end delivery of high-quality silicon.

Responsibilities

• Hire and mentor junior engineers to build and grow the design team.
• Solve SoC design challenges involving Clock, Reset, Power, and DFT.
• Collaborate with architects and micro-architects to meet PPA metrics and delivery timelines.
• Partner with verification teams to review test plans and debug design issues.
• Work with implementation teams to optimize designs for power and timing.

Required Skills

• 5+ years of experience leading RTL design for complex SoC development.
• Proficiency in Verilog and/or SystemVerilog.
• Expertise in Static Design Checks, Synthesis, and timing analysis.
• Deep knowledge of Power management techniques and Power/Clock domain crossing.
• Practical experience with processor-based system designs and computer architecture fundamentals.
• Scripting proficiency in TCL, Perl, or Python.
• Proven experience in technical team leadership, mentoring, or coaching.
• Degree in any graduate field.

Preferred Skills

• Experience with Arm-based designs or Arm System Architectures.
• Subsystem integration experience for PCIe, UCIe, DDR/LPDDR/HBM, or Ethernet.
• Programming experience in C/C++ or assembly language.
• Knowledge of embedded operating systems, device drivers, and microprocessor architectures.

Key Skills

Education

Any Graduate