Description

You will architect and build verification environments for IPs and SoCs featuring embedded CPUs and analog mixed-signal interfaces.

This role is on-site.

Responsibilities

• Architect verification environments using SystemVerilog and UVM.
• Develop test plans and coverage metrics derived from specifications, including block and chip-level tests.
• Write Perl or Python scripts to automate environment creation, test generation, and debugging.
• Perform failure analysis on RTL and gate-level simulations and resolve issues with design engineers.
• Create low power testcases using UPF or CPF to verify SoC power intent.

Required Skills

• 7+ years of experience in pre-silicon design verification.
• Proficiency in Verilog-HDL, SystemVerilog, and C-shell scripting.
• Strong knowledge of SV Assertions, UVM/OVM, and functional code coverage.
• Experience with SoC verification using ARM Cortex Microcontrollers.
• Hands-on experience with peripheral bus Verification IPs including GPIO, UART, SPI, SW, JTAG, and I2C.
• Proficiency with Cadence tools such as NCVerilog, NCSIM, and Simvision.
• Experience with SDF annotated simulations and understanding of parasitic delays and timings.

Preferred Skills

• Experience using linting tools like Spyglass.

Key Skills

Education

Not specified