Description

Architect and build verification environments for IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.

Architect and build verification environments using SystemVerilog and UVM for IPs and SoCs. Develop test plans and coverage metrics derived from specifications. Write block and chip-level tests to ensure functional coverage. Create Perl and Python scripts to automate environment setup, test generation, and debugging. Perform failure analysis on RTL and Gate simulations and resolve issues with design engineers.

Responsibilities

• Architect verification environments using SystemVerilog and UVM for IPs and SoCs.
• Develop test plans and coverage metrics derived from specifications.
• Write block and chip-level tests to ensure functional coverage.
• Create Perl and Python scripts to automate environment setup, test generation, and debugging.
• Perform failure analysis on RTL and Gate simulations and resolve issues with design engineers.

Required Skills

• 7+ years of experience in pre-silicon design verification.
• Proficiency in Verilog-HDL and SystemVerilog.
• Strong knowledge of SV Assertions, UVM/OVM, and functional code coverage.
• Experience with advanced peripheral bus Verification IPs including GPIO, UART, SPI, SW, JTAG, and I2C.
• Proficiency with Cadence tools including NC Verilog, NCSIM, and Simvision.
• Experience with C-shell scripting.
• Scripting expertise in Perl and Python.

Preferred Skills

• Experience with linting tools such as Spyglass.

Key Skills

Education

Not specified