Description

Lead mixed-signal IC development from initial specification through product introduction, owning circuit design, simulation, and characterization.

This role is on-site.

Responsibilities

• Develop detailed circuit specifications and design transistor-level topologies for mixed-signal circuits.
• Optimize circuit performance via simulation using Cadence EDA tools across various process and operating conditions.
• Provide guidance for physical layout implementation of high-speed circuits and integrate elements into large analog/mixed-signal ASICs.
• Participate in characterization and testing, building test chips and validating designs to ensure performance requirements are met.

Required Skills

• 5+ years of experience in all phases of multiple IC developments.
• Thorough knowledge of high-frequency, broadband Analog Mixed-Signal IC design.
• Expertise in chip top-level logic and physical design, including timing-aware logical partitioning and floor planning.
• Proficiency in analog and mixed-signal modeling and verification for complex ICs.
• Solid understanding of Cadence RTL, STA, and SDF gate-level verification flows.
• Experience with standard and custom cell/IP library build, characterization, and release processes.
• Skilled in IC characterization using high-speed sampling oscilloscopes, spectrum analyzers, VNAs, and signal sources.
• Deep understanding of PDK components and Hard IP integration methodologies.

Preferred Skills

• Experience with CMOS FinFET (16nm or lower) design.
• Proficiency in Verilog or Verilog-A modeling.

Key Skills

Education

Any Graduate