← Back to jobs

Safran Logo
R&D Engineer (FPGA Equalization)

Safran

 

91940 Les Ulis, France

Posted On: 30+ days ago
Experience: 5+ years
Availability: Hybrid
Openings: 1
Category: R&D Engineer
Tenure: No Preference/Any
Related Jobs

No related jobs found

Description

Final year master's internship focused on implementing equalization algorithms on FPGA platforms for high-speed optical data links.

Responsibilities

  • Review the state of the art regarding equalization algorithms for spatial optical data links.
  • Analyze and translate existing Matlab implementations into FPGA-targeted designs.
  • Refine algorithms to meet specific hardware constraints including FPGA clock, upstream parallelization, sampling, and quantization.
  • Implement algorithms using VHDL or via C implementation and HLS synthesis.
  • Measure performance using an optical bench representative of trans-atmospheric links.

Required Skills

  • Currently completing a final year engineering or master's degree.
  • Proficiency in VHDL.
  • Proficiency in Matlab.
  • Knowledge of FPGA technologies and hardware constraints.
  • Ability to understand and work within a digital reception chain.

Key Skills
Education

master's degree

Related Jobs

No related jobs found

← Back to jobs