Description

You will be responsible for bringing up emulation cutdowns for large SoC/IP blocks to improve emulation performance and turnaround time.

Responsibilities

• Own and bring up emulation cutdowns for large SoC/IP blocks to improve emulation performance and turnaround time.
• Adapt and port test benches to run efficiently on hardware emulation platforms.
• Debug and resolve issues related to AVIPs and transactors within the emulation environment.
• Lead bring-up and setup on Palladium and Zebu emulation platforms.
• Release validated emulation cutdowns and test benches to Software, DV, or STA teams.

Required Skills

• 6+ years of experience in RTL Design/Verification & Hardware Emulation.
• Hands-on experience with Cadence Palladium and/or Synopsys Zebu.
• Proficiency in SystemVerilog, UVM, Python, Perl, and Shell.
• Strong debugging skills, including AVIP and transactor development.
• Understanding of SoC architecture and verification methodologies.
• Experience with waveform tools like Verdi or DVE.
• Analytical and detail-oriented approach to hardware debugging.

Key Skills

Education

Any Graduate