Description

You will bring up and optimize emulation cutdowns for large SoC and IP blocks to improve performance and turnaround time.

This role is on-site.

Responsibilities

• Lead bring-up and setup on Cadence Palladium and Synopsys Zebu emulation platforms.
• Adapt and port test benches to run efficiently on hardware emulation environments.
• Debug and resolve issues related to AVIPs and transactors within the emulation setup.
• Release validated emulation cutdowns and test benches to Software, DV, or STA teams.

Required Skills

• 6+ years of experience in RTL Design, Verification, and Hardware Emulation.
• Hands-on experience with Cadence Palladium and/or Synopsys Zebu.
• Proficiency in SystemVerilog and UVM.
• Scripting skills in Python, Perl, and Shell.
• Strong debugging skills, including AVIP and transactor development.
• Understanding of SoC architecture and verification methodologies.
• Experience with waveform tools like Verdi or DVE.

Preferred Skills

• Analytical and detail-oriented approach to hardware debugging.

Key Skills

Education

Any Graduate