Description

You will own low-power RTL design and top-level SoC integration.

This role is on-site.

Responsibilities

• Execute low-power design using UPF methodologies.
• Manage SoC-level clock and reset architectures.
• Perform top-level integration of system buses, peripherals, and ARM cores.
• Handle connectivity integration and repeater implementation.
• Validate designs against CDC, RDC, and LINT requirements.

Required Skills

• 4+ years of experience in RTL Design.
• Strong expertise in Low-power Design.
• Hands-on experience with UPF.
• Proficiency in CDC, RDC, and LINT analysis.
• Experience with SoC-level Clock and Reset design.
• Knowledge of DFT principles.
• Experience integrating ARM cores, system buses, and peripherals.

Key Skills

Education

Any Graduate