Description

Define, model, and implement RTL for advanced PLL IPs and drive ASIC design flows from specification to silicon.

This role is on-site.

Responsibilities

• Analyze complex digital design problems and propose architectural solutions.
• Develop Verilog RTL and Functional Behavioral Models for current and future IPs.
• Create microarchitecture specifications and drive ASIC design flows with supporting scripts.
• Collaborate with Design Verification and Physical Design teams to ensure functional correctness, timing closure, and proper implementation.
• Deliver design improvements, optimization, and power-saving enhancements, and support silicon bring-up and diagnostics.

Required Skills

• 5+ years of progressive experience in RTL Design.
• Strong proficiency in Verilog and RTL design methodologies.
• Experience analyzing complex digital design problems and driving tasks independently to completion.
• Ability to mentor junior engineers and communicate effectively within a team.
• Master's degree in Engineering preferred.

Preferred Skills

• Proven experience in analog mixed-signal design from specification to silicon.
• Experience with high-speed interfaces (DDR, GDDR, HBM, SERDES) and designs involving multiple power or clock domains.
• Familiarity with industry-standard ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, and power estimation.

Key Skills

Education

Any Graduate