Description

You will lead the design and development of RTL code for DDR blocks using Verilog HDL to ensure functional correctness and reusability.

Responsibilities

• Design and develop RTL code for DDR blocks in Verilog HDL for various configurations.
• Conduct technical design reviews via presentations to peers and management.
• Oversee synthesis and netlist delivery to meet timing, area, and power requirements.
• Collaborate with physical design teams to assist in implementation.
• Work with Design Verification teams to define architecture and implement design processes.

Required Skills

• 10+ years of experience in the ASIC design industry.
• Expertise in the full ASIC design cycle, including spec requirements, RTL design, and design verification.
• Proficiency in Verilog HDL and RTL design.
• Experience with DDR and High Speed IO.
• Hands-on knowledge of ASIC design, synthesis, and computer architecture.
• Competency with EDA tools and Unix/Linux environments.
• Ability to handle floor-planning, timing closure, power intent, and post-silicon validation.
• Scripting skills for design automation.

Preferred Skills

• Experience with HBM, GDDR memory PHYs, USB, PCIe, SATA, or Ethernet controllers.
• Proficiency in Tcl, Perl, or Ruby scripting.
• Experience with large digital ASIC projects and front-end EDA flows.

Key Skills

Education

Any Graduate