Description

You will design and debug Verilog/RTL for IP or SoC components, owning large IP block architecture.

Responsibilities

• Design Verilog/RTL for IP or SoC components using digital logic concepts.
• Architect and implement large IP blocks.
• Debug designs using Synopsys, Cadence, or Mentor simulation tools.
• Apply SoC architecture knowledge, including std-cells and IO blocks.

Required Skills

• 3-7 years of experience in Verilog/RTL design.
• Strong command of digital logic design concepts.
• Hands-on experience with at least one large IP block.
• Proficiency with Synopsys, Cadence, or Mentor simulation and debugging tools.
• In-depth knowledge of IP block design and architecture.
• Understanding of basic SoC architecture, std-cells, and IO blocks.
• Bachelor’s or Master’s degree in Electronics Engineering, VLSI, or Microelectronics.

Preferred Skills

• Perl or Tcl scripting and automation knowledge.
• Experience in RTL logic synthesis, SDC, and constraint writing.

Key Skills

Education

Masters/ Bachelor’s degree