Description

You will design and implement RTL for advanced PLL IPs.

Responsibilities

• Define, specify, model, and implement RTL for advanced PLL IPs.
• Develop Verilog RTL and functional behavioral models.
• Create microarchitecture specifications and drive ASIC design flows and scripts.
• Collaborate with Design Verification and Physical Design teams to ensure functional correctness and proper implementation.
• Support silicon bring-up, diagnostics, and implement power-saving enhancements.

Required Skills

• 5+ years of progressive experience in RTL design.
• Proficiency in developing Verilog RTL and functional behavioral models.
• Experience with ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, and power estimation.
• Strong analytical and critical thinking skills for solving complex digital design problems.
• Ability to drive tasks independently and mentor junior engineers.
• Relevant academic background.

Preferred Skills

• Experience in analog mixed-signal design from specification to silicon.
• Experience with high-speed interfaces such as DDR, GDDR, HBM, or high-speed SERDES.
• Experience with designs involving multiple power and clock domains or advanced FinFET technologies.

Key Skills

Education

Any Graduate