Description

Design and implement RTL for advanced PLL IPs, owning the flow from specification to silicon.

This role is on-site.

Responsibilities

• Define microarchitecture specifications and drive ASIC design flows for advanced PLL IPs.
• Develop Verilog RTL and functional behavioral models to ensure design integrity.
• Collaborate with Design Verification and Physical Design teams to guarantee functional correctness.
• Support silicon bring-up, diagnostics, and implement power-saving enhancements.

Required Skills

• 5+ years of progressive experience in RTL design.
• Proficiency in developing Verilog RTL and functional behavioral models.
• Hands-on experience with ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, and power estimation.
• Strong analytical and critical thinking skills for solving complex digital design problems.
• Ability to drive tasks independently and mentor junior engineers.

Preferred Skills

• Experience in analog mixed-signal design from specification to silicon.
• Experience with high-speed interfaces such as DDR, GDDR, HBM, or high-speed SERDES.

Key Skills

Education

Any Graduate