Description

You will focus on Analog Mixed Signal verification tasks within a design environment.

Responsibilities

• Execute AMS verification using SystemVerilog and UVM.
• Perform co-simulation involving both RTL and Spice.
• Verify analog blocks through detailed modeling and simulation.

Required Skills

• 5+ years of experience in AMS (Analog Mixed Signal) verification.
• Proficiency in SystemVerilog and UVM.
• Hands-on experience with co-simulation (RTL + Spice).
• Strong understanding of analog blocks.
• Any Graduate degree.

Preferred Skills

• Experience with WREAL, RNM, or Vams modelling.

Key Skills

Education

Any Graduate