Description

You will own the verification of Analog Mixed Signal designs, ensuring correct behavior of both digital and analog components.

This role is on-site.

Responsibilities

• Execute AMS verification using SystemVerilog and UVM methodologies.
• Perform co-simulation involving both RTL and Spice models.
• Verify analog blocks through detailed modeling and simulation.
• Develop and maintain verification environments for mixed-signal IP.
• Collaborate with design teams to resolve verification gaps.

Required Skills

• 5+ years of experience in AMS (Analog Mixed Signal) verification.
• Proficiency in SystemVerilog and UVM.
• Hands-on experience with co-simulation (RTL + Spice).
• Strong understanding of analog block behavior and modeling.
• Any Graduate degree.

Preferred Skills

• Experience with WREAL, RNM, or Vams modelling.

Key Skills

Education

Any Graduate